The present invention relates to the design of integrated circuits, and more specifically, to methods and systems for modeling and simulating the impact of imperfectly fabricated vias and redundant via arrays on the performance and reliability of an integrated circuit.
The age of information and electronic commerce has been made possible by the development of electronic circuits and their miniaturization through integrated circuit technology. Integrated circuits are sometimes referred to as “chips” or “ICs.”
To meet the challenges of building more complex and higher performance integrated circuits, various specialized software tools are used. These tools exist in one or more areas commonly referred to as; computer aided design (CAD), computer aided engineering (CAE), electronic design automation (EDA), or technology computer aided design (TCAD).
There is a constant need to improve these tools for each technology generation in order to address the requirements for; higher integration, greater functional capability and complexity, smaller chip area, and better performance of integrated circuits. Additionally, driven by technology requirements, certain tools and capabilities developed in the TCAD domain, traditionally focused on small-scale advanced technology development, are moved and recast for the large-scale EDA domain in order to address more sophisticated effects as they become more significant in IC design.
At the same time and despite significant increase in logic function and complexity, for each technology generation, inherent manufacturability, yield, and reliability must be maintained or improved and specialized design for manufacturability (DFM) tools are necessary and must be used in integrated circuit design flows for this purpose. These tools are typically and primarily driven by the photolithographic patterning and pattern transfer processes which enable miniaturization for each successive process generation but do so with limited patterning fidelity. As such, these tools have primarily been focused on optimizing the geometrical shape fidelity of the features defining the physical circuit in the lateral planes of the manufactured chip. To achieve this, highly planar layers are required as well and great effort is expended to add dummy features to aid in planarization with the unavoidable consequence of greater parasitic coupling of signals to the dummy features. These inherent nanoscale technology effects and others mandate greater analysis of these non-idealized shapes and dummy features to determine and minimize their impact on the functional performance of the IC.
When DFM tools are primarily driven by electrical function metrics rather than geometrical shape, they are often referred to as electrically-driven DFM (eDFM) tools. eDFM tools are typically limited by circuit simulator capacity and runtime constraints as well as the large number of non-ideal physical features which must be considered in such a methodology for accurate results.
As IC interconnect, via, and device critical dimensions are reduced and/or system frequency is increased many additional so-called “parasitic” RLC effects must be considered. These parasitic effects can cause unwanted cross-coupling of signals, a reduction in signal voltage, or reduction or noise in signal, clock, and power distribution networks. These effects should properly be accounted for in simulation of the IC. If not, there is increased risk that the IC will have functional failure or performance limitations following fabrication and incorporation into an end product. The number of parasitic effects has been increasing for each process generation and with increases in circuit size, complexity, and function simulating the impact of these parasitics is an enormous challenge requiring very large computing resources and time. The variation in not only the fine line wire interconnects but also the vias which interconnect these wires fall within this category and we are primarily focused on the influence of via variations on the electrical performance of an IC in this documents.
Myriad variations impact integrated circuit performance and reliability and should be accounted for in any robust integrated circuit design flow. For nanoscale IC designs, in general, variations occur in many forms and their impact on the IC function may be very non-intuitive. These variations occur even for a well-controlled fabrication processes simply due to fundamental physical limits dictating the resolution, planarity, or homogeneity of the physical circuit elements. Patterned features are far from ideal resulting in geometrical feature distortions and variations in the distributed resistance, capacitance, and resistance of clock, signal, or power network. Inter-layer dielectric and metal layer thickness variations also occur and further compound the problem difficulty. Additionally, intrinsic variations due to fundamental material properties include statistical material inhomogneities of the various layers comprising the integrated circuit and may impact interconnect as well as active devices such as for example through deposited material inhomogeneity and statistical dopant fluctuation. Variations may also be exhibited in either/both intra-die or inter-die manner, meaning that the variations may be the same for each die or different for each die across the wafer of dice. An example of the former is due to pattern-dependent proximity effects such as from the photolithography process wherein constructive and destructive interference effects occurring during partially-coherent imaging causes critical feature shape variations. Examples of the latter include deposition or etch chamber effects impacting the across-wafer uniformity of a given process. These effects may also be time-varying as well. These variations increasingly must be accounted for during a well designed IC to reduce functional sensitivity to inherent variations in the fabrication of the IC.
Interconnect problems for large ICs manufactured with nanoscale technology are known to contribute to significant chip failures and performance reduction and are a key concern in IC design. There are many factors that must be considered and addressed in order to ensure a robust inherently high-yielding and reliable design. One such factor which is critical is associated with via or contact failures or marginal high resistance vias. These may be significant factors in chip failures, performance reduction, or in-field reliability. Both signal and power nets are impacted. A typical integrated circuit includes an enormous number of vias connecting the various metal layers of an IC or which contact the silicon device and the complete failure or partial failure (e.g., leading to a higher than expected resistance) of any one or number of vias in a series can lead to a failure or reduction in reliability of the chip.
Vias are found in all integrated circuits including digital signal processors (DSPs), amplifiers, dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), Flash memories, microprocessors (e.g., CPUs), graphic processors (e.g., GPUs), physics processors, embedded processors (e.g., ARM and MIPS cores), application specific integrated circuits (ASICs), and programmable logic. However, the problem is typically most severe for large area ICs which typically have long wire lengths.
Vias or via arrays for the lower metal levels of an IC are among the most lithographically sensitive structures in a nanoscale integrated circuit. Lithographically resolving these features is not only is it an enormous process challenge but pattern fidelity and dimensional tolerances are particularly highly susceptible to small photomask errors due to the mask error factor (MEF) effect wherein the error of a mask is greatly amplified for these features further compounding the problem. But even further compounding the problem is the lithographic focus latitude dictating a very small acceptable process window over which acceptable lithographic patterning will occur. As a result of these patterning difficulties as well as other associated process variations, such as with deposition and etch, vias used for supplying a stable constant voltage to the internal active devices or transmitting critical clock or logic signals of an integrated circuit can be significantly different from ideal extraction assumptions. Consequently, critical voltage and current values distributed throughout the IC may easily fall out of the designer's desired specified range. For example, they may have significantly higher resistance than typically assumed by electronic design automation (EDA) extractors, they may be more highly variable, and they may even conduct current in a manner which is not well considered by designers. These and other factors now make vias a principle current-resistance (IR) drop and electromigration (EM) yield-limiting mechanism which must be considered far more rigorously than in past process technology generations.
Both via-based IR drop and current-density induced electromigration can be significant causes of yield loss necessitating costly silicon respins. A small drop in VDD or increase in local ground voltage can severely impact leakage or clock speed performance in low-voltage designs, so it is imperative to have well-controlled voltage down to the transistor level. To improve reliability and reduce current density, redundant vias are commonly used, however the methodology for insertion and verification is often dictated by heuristic rules or based on test structures rather than rigorous analysis of the actual circuit.
Clock and logic signal wiring typically do not use a large degree of redundant vias for reasons of performance. The tradeoff can be reduced reliability as current density is increased and the impact of via size variations can have a much greater impact.
In terms of capacity, the vast number of real drawn vias in a typical modern integrated circuit may be orders of magnitude beyond what most existing circuit simulation tools are capable of. So it has not been possible to accurately assess the impact of vias on large circuits due to capacity and speed limitations of SPICE-accurate simulators. As a result, vias and redundant via arrays are typically simplified in a network which results in underestimating the resistance, variability, and limiting the accuracy of the result.
While vias in traditional IC technology are used to connect different layers on side of an IC they are also used to connect layers which exist on both sides of an IC and to connect stacked ICs. In this mode, these vias are typically called through-silicon vias (TSVs). By use of TSVs three-dimensional integrated circuits, or 3D-ICs, are created. Both signals and power may be connected through the use of TSVs connecting different ICs in a 3D-IC. An added difficulty with TSVs over conventional vias is associated with potential substrate current injection.
Therefore, what is needed is a system and technique to enable simulation-based verification of vias and via arrays in an accurate and nonreduced manner to confirm satisfactory IR drop and current density over a range of typical manufacturing conditions. Moreover in the event of an error, the simulation tools should provide a direct one-to-one layout isolated view of the error to enable quick analysis and repair. Further, what is also needed are tools which enable enormous capacity and speed without resorting to accuracy-reducing compromises.